代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/139799/13130436
vhd example16-4.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY counter IS
PORT (
clk: IN std_logic;
reseta: IN std_logic;
resetb: IN
www.eeworm.com/read/326570/13134715
vhd cnt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
port(clk,ld:in std_logic;
d:in std_logic_vector(13 downto 0);
q:buffer std_logic_vec
www.eeworm.com/read/139685/13139914
txt mealy1.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/139685/13139918
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/139685/13139931
txt moor1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/139685/13139937
txt moor2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/326024/13169824
vhd cnta.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNTA IS
PORT ( CLK : IN STD_LOGIC;
U_D : IN STD_LO
www.eeworm.com/read/325800/13184126
vhd and4.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity and4 is
port (
a: in STD_LOGIC;
b: in STD_LOGIC;
c: in STD_LOGIC;
d: in STD_LOGIC;
y: out STD_LO
www.eeworm.com/read/325800/13184149
keyscan66
-- KEY BOARD
-------------------------------------
--000 *A* *B* *C* *D* *E* *F*
--001 *G* *H* *I* *J* *K* *L*
--010 *M* *N* *O* *P* *Q* *R*
--011 *S
www.eeworm.com/read/240876/13189751
vhd comcoun.vhd
--comcoun.vhd 7 segment com scan counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comcoun is
port(
clk : in std_logic;--synchronouse clock
f1k