代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/327323/13086803
vhd mc8051_ram_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/327323/13086863
vhd alumux_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/327323/13086932
vhd mc8051_alu_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/327323/13086941
vhd mc8051_siu_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/326700/13121965
doc vhdljianfaqi1.doc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jian4 is
port
( a: in unsigned(3 downto 0);
b: in unsigned(3 d
www.eeworm.com/read/326700/13121967
doc vhdljianfaqi.doc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jian4 is
port
( a: in unsigned(3 downto 0);
b: in unsigned(3 d
www.eeworm.com/read/326697/13122060
doc vhdlsiweiquanjiaqqi.doc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity four is
port
( a: in unsigned(3 downto 0);
b: in unsigned(3 downto 0);
ci
www.eeworm.com/read/241626/13128724
vhd mctrl.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is
www.eeworm.com/read/241625/13128734
vhd fp.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is
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vhd example16-2.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY counter16 IS
PORT (
clk: IN std_logic;
reseta: IN std_logic;
resetb: I