vhdlsiweiquanjiaqqi.doc

来自「这是一个利用MAX PULL 制作的VHDL的四位全加器的程序 如果有需要仿真图」· DOC 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity four is
port	
( a: in unsigned(3 downto 0);
  b: in unsigned(3 downto 0);
   cin: in std_logic;
  bcdout: out std_logic_vector(3 downto 0);
  cout: out std_logic  );
end four;
architecture arch of four is
   signal y,c:std_logic_vector(3 downto 0);
begin 
      y(0)<=a(0) xor b(0) xor cin;
      y(1)<=a(1) xor b(1) xor c(0);
      y(2)<=a(2) xor b(2) xor c(1);
      y(3)<=a(3) xor b(3) xor c(2);
      c(0)<=(cin and a(0)) or (cin and b(0)) or (a(0) and b(0));
      c(1)<=(c(0)and a(1)) or (cin and b(1)) or (a(1) and b(1));
      c(2)<=(c(1)and a(2)) or (cin and b(2)) or (a(2) and b(2));
      c(3)<=(c(2)and a(3)) or (cin and b(3)) or (a(3) and b(3));
      bcdout<=y(3)&y(2)&y(1)&y(0);
      cout<=c(3);
end arch;