代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/197597/7984813
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/197597/7984820
txt 带莫尔1米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/197597/7984832
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/297535/8012276
vhd sysctrl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY sysctrl IS
PORT( clk1 : IN STD_LOGIC;
clk2 : IN STD_LOGIC;
clk3 : IN STD_LOGIC;
clk4 : IN STD_LOGIC;
www.eeworm.com/read/196997/8036559
txt 4位10进制计数器vhdl程序.txt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in std_logic;
reset : in std_logic;
www.eeworm.com/read/196954/8038872
vhd adtofifo.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Entity Declaration
ENTITY AdToFifo IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LIN
www.eeworm.com/read/297219/8043823
bak counter1.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter1 is
port(
clk: in std_logic;
enable: in std_logic;
load:
www.eeworm.com/read/296373/8108693
vhd hdb3c.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3c is
port(reset,clk: in std_logic;
datain: in std_logic_vector(1 downto 0);
dout: out std_logic
www.eeworm.com/read/196115/8114488
vhd regfile.vhd
--****************************************************************************************************
-- Register file for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 23.01.2003
--******
www.eeworm.com/read/196115/8114539
vhd alu.vhd
--****************************************************************************************************
-- ALU for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 16.12.2002
--****************