代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/198555/7927770
vhd mc8051_siu_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/398445/7946220
vhd hour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(reset,clk:in std_logic;
daout:out std_logic_vector(7 downto 0));
end hour;
architecture behave o
www.eeworm.com/read/198238/7946367
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/398445/7946396
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port(reset,clk,setmin:in std_logic;
enmin:out std_logic;
daout:out std_logic_vector(7 downto 0));
www.eeworm.com/read/398445/7946454
vhd minute.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute is
port(reset,clk,sethour:in std_logic;
enhour:out std_logic;
daout:out std_logic_vector(7 downto 0));
www.eeworm.com/read/198238/7946473
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/198238/7946487
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/198238/7946528
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/297990/7982478
vhd decoder.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Decoder is
PORT(
D : in std_logic_vector(31 downto 0);
C : out std_logic_vector(2 downto 0);
flag : out std_logic_vector(1
www.eeworm.com/read/197597/7984764
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in