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Logic Analyzer 的代码
logic.lso
work
logic.sym
VERSION 5
BEGIN SYMBOL logic
SYMBOLTYPE BLOCK
TIMESTAMP 2006 3 31 0 55 18
SYMPIN 416 176 Input M0UART
SYMPIN 176 176 Output UART0
SYMPIN 416 208 Input M1UART
SYMPIN 416 240 Input M2UART
SYMPIN
logic.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
logic.prj
vhdl work logic.vhd
logic.syr
Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.48 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to