logic.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : xil_800_4
-- /___/   /\     Timestamp : 03/31/2006 08:55:26
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: logic
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity logic is
   port ( Addr1  : in    std_logic; 
          Addr2  : in    std_logic; 
          ALM0   : in    std_logic; 
          ALM1   : in    std_logic; 
          ALM2   : in    std_logic; 
          CLK8   : in    std_logic; 
          CS_U   : in    std_logic; 
          INT_L0 : in    std_logic; 
          M0UART : in    std_logic; 
          M1UART : in    std_logic; 
          M2UART : in    std_logic; 
          ALM_R  : out   std_logic; 
          CLK    : out   std_logic; 
          INT0   : out   std_logic; 
          UART0  : out   std_logic);
end logic;

architecture BEHAVIORAL of logic is
--signal ts:  std_logic;
signal ad2: std_logic_vector (1 downto 0);
begin
 INT0<=INT_L0;
 CLK<=CLK8;
 ALM_R<=ALM0 or ALM1 or ALM2;
 ad2<=addr2 & addr1; 
 process (ad2,CS_U,M0UART,M1UART,M2UART)
   begin
   if(CS_U='0') then
	 UART0<='1';
	 else	
	   case ad2 is
	    when "00"=>UART0 <=M0UART;
 		 when "01"=>UART0 <=M1UART;
 		 when "10"=>UART0 <=M2UART;
       when others =>UART0 <='1'; 
      end case;
	end if;
 end 	process;
-- with ad2 select
--	UART0<=M0UART when 00
end BEHAVIORAL;

-- synopsys translate_off
configuration CFG_logic of  logic is
   for BEHAVIORAL
   end for;
end CFG_logic;
-- synopsys translate_on