代码搜索：LP
找到约 9,457 项符合「LP」的源代码
代码结果 9,457
www.eeworm.com/read/368546/9689872
c lp_dec2.c
/*-------------------------------------------------------------------*
* LP_DEC2.C *
*-------------------------------------------------------------------*
* Decim
www.eeworm.com/read/366988/9786256
v lp_division1.v
`timescale 1ns/10ps
module lp_division1(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@(
www.eeworm.com/read/366988/9786294
v lp_division7.v
`timescale 1ns/10ps
module lp_division7(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@(
www.eeworm.com/read/366988/9786301
v lp_division8.v
`timescale 1ns/10ps
module lp_division8(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@(
www.eeworm.com/read/366988/9786305
v lp_division10.v
`timescale 1ns/10ps
module lp_division10(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@
www.eeworm.com/read/366988/9786307
v ffd_lp_18.v
`timescale 1ns/10ps
module FFD_lp_18(data,clock,reset,q);
output [18:1] q;
input clock,reset;
input [18:1] data;
FFD_lp f1(data[1],clock,reset,q[1]),
www.eeworm.com/read/366988/9786308
v lp_division3.v
`timescale 1ns/10ps
module lp_division3(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@(
www.eeworm.com/read/366988/9786309
v lp_division2.v
`timescale 1ns/10ps
module lp_division2(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@(
www.eeworm.com/read/366988/9786317
v lp_division4.v
`timescale 1ns/10ps
module lp_division4(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@(
www.eeworm.com/read/366988/9786318
v lp_division9.v
`timescale 1ns/10ps
module lp_division9(data_in,clock,reset,data_out);
input [19:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [38:1] temp_data;
always@(