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period_led.cdf

/* Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EP1C6Q240) Path("") File("period_led.s

period_led.pss

| 27826d7056b1525e5443c56e1a11bc47

period_led.hif

Version 7.0 Build 33 02/05/2007 SJ Full Version 35 1941 OFF OFF OFF OFF ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- --

period_led.pin

-- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

period_led.qws

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 ptn_Child3=Document-2 [P

period_led.v

module period_led(LED,CLK); input CLK; output[7:0] LED; reg [7:0] LED; reg [23:0] counter; always @(posedge CLK) //在时钟负延跳变,也就是计数什么的 begin counter