代码搜索：Key1
找到约 1,573 项符合「Key1」的源代码
代码结果 1,573
www.eeworm.com/read/17895/766327
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/17904/766416
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/17921/767304
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/18031/771559
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/18253/782509
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/18342/784927
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/18488/791228
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/296366/3904400
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/369325/9654863
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec
www.eeworm.com/read/248277/12586422
vhd key1.vhd
--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key1 is
port(
kin:in std_logic;
kout:out std_logic_vector(1 downto 0)
);
end key1;
architec