key1.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册所配套源代码」· VHDL 代码 · 共 24 行

--Key1模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity key1 is 
port(
	kin:in std_logic;
	kout:out std_logic_vector(1 downto 0)
);
end key1;

architecture beh of key1 is
begin
	process(kin)
	variable count:std_logic_vector(1 downto 0);
	begin
		wait until kin'event and kin='0';
		count:=count+'1';
		kout<=count;
	end process;
end beh;