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/****************************************************************************** * * LOGIC CORE: Control Interface - Top level module * MODULE NAME: control_interface() * COM

$ Start of Compile #Mon Jul 19 18:36:03 2004 Synplicity VHDL Compiler, version 7.1, Build 158R, built Apr 18 2002 Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved VHDL syntax chec

(edif (rename uc_interface "uC_interface") (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2004 7 19 18 36 4) (author "Synpli

@P: Worst Slack : 989.769 @P: clk - Estimated Frequency : 97.7 MHz @P: clk - Requested Frequency : 1.0 MHz @P: clk - Estimated Period : 10.231 @P: clk - Requested Period : 1000.000 @P: clk

# # Constraints generated by Synplify Pro 7.1, Build 152R # # Period Constraints #Begin clock constraints #End clock constraints # Output Constraints # Input Constraints # Location Con

@E"VRMNFMl;C"RHyVDjCR "VR8#:\$DMbH0OH$$\#MHbDV($_4H\DLE\P80\#8E3P8R";yDVHC R4V8R":$\l_#8CH\oMH\.O#sFkOkC\b0OMcE3P8R";yDVHC R.V8R":$\#MHbDO$H0\M#$bVDH$4_(\LDH\8PE\8#04c4n38PE"y;RVCHDRVd R:"8\M#$bOD

fsm_encoding {818321831} sequential fsm_state_encoding {818321831} idle {00} fsm_state_encoding {818321831} addr {01} fsm_state_encoding {818321831} data_trs {10} fsm_state_encoding {818

f "noname"; #file 0 f "d:\synplicity\synplify_71\lib\vhd\std.vhd"; #file 1 f "d:\my_design\i2c\source\upcnt4.vhd"; #file 2 f "d:\synplicity\synplify_71\lib\vhd\std1164.vhd"; #file 3 f "d:\synplici

Synthesizing work.uc_interface.behaviour @N:"D:\My_Design\I2C\source\uc_interface.vhd":111:16:111:17|Using sequential encoding for type state_type @W:"D:\My_Design\I2C\source\uc_interface.vhd":267:3

# # # # Created by Synplify VHDL Compiler version 7.1, Build 158R from Synplicity, Inc. # Copyright 1994-1999 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Mon Jul 19 18: