uc_interface.plg

FPGA-CPLD_DesignTool(8-9-10)源代码

@P:  Worst Slack : 989.769
@P:  clk - Estimated Frequency : 97.7 MHz
@P:  clk - Requested Frequency : 1.0 MHz
@P:  clk - Estimated Period : 10.231
@P:  clk - Requested Period : 1000.000
@P:  clk - Slack : 989.769
@P:  System - Estimated Frequency : 108.2 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 9.238
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 990.762
@P: uC_interface Part : xc2s15cs144-5
@P: uC_interface I/O primitives : 81
@P: uC_interface I/O Register bits : 22
@P: uC_interface Register bits (Non I/O) : 23 (5%)
@P: uC_interface Total Luts : 57 (14%)