代码搜索:ISE教程

找到约 10,000 项符合「ISE教程」的源代码

代码结果 10,000
www.eeworm.com/read/318858/3561591

bld fpga_lcm.bld

Release 6.2i - ngdbuild G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\lcm\ise\lcm/_n
www.eeworm.com/read/318858/3561642

bld rom_32x8.bld

Release 6.2i - ngdbuild G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\lcm\ise\lcm/_n
www.eeworm.com/read/318858/3561853

bld i2c.bld

Release 6.2i - ngdbuild G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\iic\ise\iic/_n
www.eeworm.com/read/444143/1736190

regkeys

ISE_VERSION_CREATED_WITH 10.1.01 s ISE_VERSION_LAST_SAVED_WITH 10.1.01 s LastRepoDir D:\simulate\work\D_BLAST44\ s OBJSTORE_VERSION 1.3 s PROJECT_CREATION_TIMESTAMP 2009-02-27T10:43:28 s REGISTRY_VERS
www.eeworm.com/read/422912/2030663

regkeys

ISE_VERSION_CREATED_WITH 10.1 s ISE_VERSION_LAST_SAVED_WITH 10.1 s LastRepoDir E:\pham thanh cong\My Documents\Bai FPGA\AD7823\ s OBJSTORE_VERSION 1.3 s PROJECT_CREATION_TIMESTAMP 2009-02-24T20:31:58
www.eeworm.com/read/418865/2082587

regkeys

ISE_VERSION_CREATED_WITH 10.1 s ISE_VERSION_LAST_SAVED_WITH 10.1 s LastRepoDir C:\Xilinx\Proyectos\VGA\ s OBJSTORE_VERSION 1.3 s PROJECT_CREATION_TIMESTAMP 2008-07-04T15:18:05 s REGISTRY_VERSION 1.1 s
www.eeworm.com/read/383754/2613863

map add_2bit_module_map.map

Release 9.1i Map J.30 Xilinx Map Application Log File for Design 'add_2bit_module' Design Information ------------------ Command Line : D:\Xilinx91i\bin\nt\map.exe -ise D:/ise_book/Example-8-2/tes
www.eeworm.com/read/361782/2943210

regkeys

ISE_VERSION_CREATED_WITH 9.1i s ISE_VERSION_LAST_SAVED_WITH 10.1 s LastRepoDir F:\MiniStep_v1.0\snapshots\snap1\ s OBJSTORE_VERSION 1.3 s PROJECT_CREATION_TIMESTAMP UNINITIALIZED s REGISTRY_VERSION 1.
www.eeworm.com/read/154076/5643080

srd top.srd

f "noname"; #file 0 f "j:\eda\synplicity\synplify_70\bin\..\lib\xilinx\virtex2p.v"; #file 1 f "j:\projects\ise\coregendemo\dpram_core_demo\dpram_core.v"; #file 2 f "j:\projects\ise\coregendemo\dpra
www.eeworm.com/read/267559/11174962

mrp fifo89_map.mrp

Release 9.1.03i Map J.33 Xilinx Mapping Report File for Design 'fifo89' Design Information ------------------ Command Line : G:\Xilinx91i\bin\nt\map.exe -ise F:/vhdl/fifos/fifo_exp1/fifo_exp1.ise