add_2bit_module_map.map

该源码为xilinx ise教程的附带光盘源码

Release 9.1i Map J.30
Xilinx Map Application Log File for Design 'add_2bit_module'

Design Information
------------------
Command Line   : D:\Xilinx91i\bin\nt\map.exe -ise
D:/ise_book/Example-8-2/test_add/test_add.ise -intstyle ise -p xcv50e-cs144-6
-cm area -pr b -k 4 -c 100 -tx off -o add_2bit_module_map.ncd
add_2bit_module.ngd add_2bit_module.pcf 
Target Device  : xcv50e
Target Package : cs144
Target Speed   : -6
Mapper Version : virtexe -- $Revision: 1.36 $
Mapped Date    : Wed Dec 27 17:39:47 2006

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             8 out of     94    8%

   Number of hard macros:           1
Total equivalent gate count for design (not including hard macros):  0
Additional JTAG gate count for IOBs:  384
Peak Memory Usage:  140 MB
Total REAL time to MAP completion:  4 secs 
Total CPU time to MAP completion:   3 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "add_2bit_module_map.mrp" for details.