代码搜索:Homework

找到约 1,174 项符合「Homework」的源代码

代码结果 1,174
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srs se_pa.srs

# # # # Created by Synplify Verilog HDL Compiler version 3.6t, Build 139R from Synplicity, Inc. # Copyright 1994-2006 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Tue No
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msg se_pa.msg

@TM:1162860178 @N: BN191 :"":0:0:0:-1|Writing property annotation file D:\Homework\ISE8.1 work\pa_ser\rev_1\Mult_tst.tap. @N: BN225 :"":0:0:0:-1|Writing default property annotation file D:\Homework\
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tlg mult_tst.tlg

Selecting top level module Mult_tst_v @N: CG364 :"D:\Homework\ISE8.1 work\Mult\Mul.v":21:7:21:10|Synthesizing module Mult @N: CG179 :"D:\Homework\ISE8.1 work\Mult\Mul.v":35:17:35:19|Removing redun
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htm mul_flink.htm

Log File Links:
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srd mult_tst.srd

f "noname"; #file 0 f "d:\software\synplify v8.6\fpga_861\lib\xilinx\unisim.v"; #file 1 f "d:\homework\ise8.1 work\mult\mul.v"; #file 2 f "d:\homework\ise8.1 work\mult\mult_tst.v"; #file 3 @EuyRsF
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tlg people4.tlg

Selecting top level module people4 @N: CG364 :"E:\Homework\ISE8.1 work\people4\people4.v":21:7:21:13|Synthesizing module people4
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srr people4.srr

#Build: Synplify 8.6.1, Build 013R, Jun 5 2006 #install: D:\Software\Synplify 8.6.1\fpga_861 #OS: Windows XP 5.1 #Hostname: UESTC-XDK #Fri Jan 19 10:08:56 2007 $ Start of Compile #Fri Jan 1
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cmd_log time_going.cmd_log

xst -ise "D:/Homework/ISE8.1 work/time24/time24" -intstyle ise -ifn time_going.xst -ofn time_going.syr xst -ise "D:/Homework/ISE8.1 work/time24/time24" -intstyle ise -ifn time_going.xst -ofn time_goi
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lst netlist.lst

D:\Homework\ISE8.1 work\time24\time_going.ngc 1162297998 OK
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lkf debug.lkf

-z -q -c -m"./Debug/I2C.map" -o"./Debug/I2C.out" -w -x -i"c:/ti/c6000/bios/lib" -i"c:/ti/c6000/rtdx/lib" -i"c:/ti/c6000/xdais/lib" -i"c:/ti/c6000/cgtools/lib" "D:\homework\document to be improve\I2C\