people4.srr

这是我自己写的4人表决器源码

#Build: Synplify 8.6.1, Build 013R, Jun  5 2006
#install: D:\Software\Synplify 8.6.1\fpga_861
#OS: Windows XP 5.1
#Hostname: UESTC-XDK

#Fri Jan 19 10:08:56 2007

$ Start of Compile
#Fri Jan 19 10:08:56 2007

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Software\Synplify 8.6.1\fpga_861\lib\xilinx\unisim.v"
@I::"D:\Software\Synplify 8.6.1\fpga_861\bin\..\lib\xilinx\unisim.v"
@I::"E:\Homework\ISE8.1 work\people4\people4.v"
@W: CS223 :"E:\Homework\ISE8.1 work\people4\people4.v":27:6:27:6|Port declaration for e specifies a range, but later declarations do not
Verilog syntax check successful!
Selecting top level module people4
@N: CG364 :"E:\Homework\ISE8.1 work\people4\people4.v":21:7:21:13|Synthesizing module people4

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan 19 10:08:57 2007

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Synplicity Xilinx Technology Mapper, Version 8.6.0, Build 246R, Built Jun 20 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.6.1
Reading constraint file: E:\Homework\ISE8.1 work\people4\people4.sdc
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
Reading Xilinx I/O pad type table from file <D:\Software\Synplify 8.6.1\fpga_861\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <D:\Software\Synplify 8.6.1\fpga_861\lib/xilinx/gttype.txt> 


@N: MF138 :"e:\homework\ise8.1 work\people4\people4.v":30:4:30:7|Rom e_1[0] mapped in logic.
@N: MO106 :"e:\homework\ise8.1 work\people4\people4.v":30:4:30:7|Found ROM, 'e_1[0]', 16 words by 1 bits 
@N: MT206 |Autoconstrain Mode is ON
@N|Only System clock will be Autoconstrained
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

xct_reducefodelay set to FALSE
Net buffering Report for view:work.people4(verilog):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
@N: FX164 |The option to pack flops in the IOB has not been specified 
Total number of merged luts: 0

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
@N: BN191 |Writing property annotation file E:\Homework\ISE8.1 work\people4\people4.tap.
Writing Analyst data base E:\Homework\ISE8.1 work\people4\people4.srm
@N: BN225 |Writing default property annotation file E:\Homework\ISE8.1 work\people4\people4.map.
Writing EDIF Netlist and constraint files
Version 8.6.1


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jan 19 10:09:00 2007
#


Top view:               people4
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    E:\Homework\ISE8.1 work\people4\people4.sdc
                       
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for people4 

Mapping to part: xc3s500efg320-4
LUT4            1 use
I/O ports: 5
I/O primitives: 5
IBUF           4 uses
OBUF           1 use

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)

Mapping Summary:
Total  LUTs: 1 (0%)

Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan 19 10:09:00 2007

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