代码搜索：Fir 开发教程
找到约 10,000 项符合「Fir 开发教程」的源代码
代码结果 10,000
www.eeworm.com/read/283083/9043799
asm fir.asm
;数字低通滤波器
;fl=1000HZ
;fs=15000Hz
;N=10
.mmregs
.global _data_start ;声明全局函数
.bss mem,100 ;定义变量 mem 存放待计算数据
.bss input,100 ;input存放输入数据
.bss output,100 ;output存放输出数据
.bss coff,
www.eeworm.com/read/185241/9047538
h fir.h
/* ==================================================================
File name : FIR.H
Originator : Advanced Embeeded Control (AEC)
www.eeworm.com/read/382086/9050517
out fir.out
www.eeworm.com/read/382086/9050525
pjt fir.pjt
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
[Project Settings]
ProjectDir="C:\ti\myprojects\Fir\"
ProjectType=Executable
CPUFamily=TMS320C67XX
Tool="Compiler"
www.eeworm.com/read/382086/9050527
c fir.c
//Fir.c FIR filter. Include coefficient file with length N
#include "bs2700.cof" //coefficient file BS @ 2700Hz
int yn = 0; //initialize filter's output
short dly[N];
www.eeworm.com/read/282817/9059092
vwf fir.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/184944/9064116
vhd fir.vhd
---------------------------------------------------------------
-- FIR Digital Filter Design (DSP example)
-- tested by Weijun Zhang, 04/2001
--
-- VHDL Data-Flow modeling
-- KEYWORD:
-- generate, a
www.eeworm.com/read/184909/9066031
qsf fir.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/184909/9066037
qpf fir.qpf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/184909/9066038
vhd fir.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.SIGNED_ARITH.all;
use work.coeffs.all;
entity fir is
port(clk,reset: in std_logic;
sample: in signed (