代码搜索：Fast

找到约 10,000 项符合「Fast」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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tcl shannon_fast.tcl

# Run with quartus_sh -t set_global_assignment -name ROOT "|shannon_fast" set_global_assignment -name FAMILY "CYCLONE" set_global_assignment -name DEVICE "EP1C3T100C6" set_global_assi
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tlg shannon_fast.tlg

Selecting top level module shannon_fast @N:"C:\prj\Chapter5\Example-5-8\source\shannon_fast.v":1:7:1:18|Synthesizing module shannon_fast
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vqm shannon_fast.vqm

// // Written by Synplify // Synplify 8.1.0, Build 539R. // Wed Mar 08 18:30:33 2006 // // Source file index table: // Object locations will have the form : // file 0 "noname" // f
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srd shannon_fast.srd

f "noname"; #file 0 f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1 f "c:\eda\synplicity\fpga_81\lib\altera\cyclone.v"; #file 2 f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #fil
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fse shannon_fast.fse

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srs shannon_fast.srs

# # # # Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Wed M
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vif shannon_fast.vif

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file shan
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srm shannon_fast.srm

@ERMRq pa)qq_uR XOCFs_RVVuv)Q;O NR 3#HPb_E_8DkR#C4N; PHR3#Hbsl;R4 RNP#_$MVOFsCC_#Js_bH"lRO"D ;P NRE3P8#D_ RHb4F; R J;HDRO N; H$R#M#_HOODF ;R4 OHRD s;N#HR$NM_#O$ME;R4 bHRsCC#0N; H$R#M#_N$EMO
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xrf shannon_fast.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cyclone.v,
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sxr shannon_fast.sxr

BeginView shannon_fast NoName Inst: un4_late_eq_1_NE_3_a_x un4_late_eq_1_NE_3_a_x_cZ stratix_lcell Inst: out_0_a2 out_0_a2_cZ stratix_lcell Inst: out_0_a2_a out_0_a2_a_cZ stratix_lcell
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