shannon_fast.srd

设计与验证verilog hdl

f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cyclone.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #file 3
f "c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v"; #file 4
f "c:\prj\chapter5\example-5-8\source\shannon_fast.v"; #file 5
VNAME 'work.shannon_fast.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDLssNH
C#uaq)Rb"C40OdOj4j-;n"

@ 
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R;N3PRsFCVDM8HoH_PCHI_8;R4
RNP3sMNCCN8ObFlR
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RNP30bNEM_O0;R.
RNP3lNDNbO_N_0EOMFk0;R4
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POR3bE_OC#O	k(lRc.n((dd(;R
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HbR3FNs0Ds8HRM"H"H;
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@FR@c6:::4ccn:4R0Fk;H
NRF3bsD0N8RHs"0Fk"o;
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(;NOMRFNlbsFN0s8_N8RCs4b;
R4@@:44::.4:+0j:sRkCfjj:Rk0sCsR0keCRB
B;NsHRCFoHMER#NFMMMN_V#;0R
@bR@44::44::j.+:DVN#fCRjR:jV#NDCNRVDR#Ct;h7
RNHsHCoF#MREMNMFVM_NR#0;R
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NRF3l84CR;H
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wjRjcjjccjjcjjjjjjjjcjjccjjccjjccjjc;H
NRF3l84CR;H
NRM3CNCLDR
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RNHsHCoF#MREMNMFVM_NR#0;R
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SNL0N=ckM_0DNCJ_C_N4__8N8c8
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SN80N=ckM_0DNCJ_C_h4_ __dN;_G
RA44y,j!?5dV5:!.4?5??5jV2:0::020R22;w
BRcjjjccjjjcjjjjjjcjjjccjjccjjccjj;cj
RNH38lFC;R4
RNH3NCMLRDCjN;
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4;NsHRCFoHMER#NFMMMN_V#;0R
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8NN0OM=H4r_O(S9
8NN08M=kdN_D0CC_J__jN__jN(88;4
AR.4,y?5d5V.?:5j*4*?45Vj?::02!2f42.:5?:fjVR22;w
BRcjjjccjjjcjjjjjjcjjjccjjccjjccjj;cj
RNH38lFC;R4
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4,R4.5y!d.?5?jV:*?544j*5?0V:2f:!4:225f.?j2:V2
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4;N3HRCLMNDjCR;H
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4,R4..y5?5j*4*?45Vj?::02!2f4:j!f2
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";N3HR#_klDOk0_bHMk.0R;H
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SFFlLkk0=MDd_N_0CCjJ__jN__8N8nO
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SNN0N=jHM_nOr98
SNL0N=.HM_nOr9O
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AR.4,y?5.j4*5?54*j:?V0!2:f:42!2fjRA;
.,R445y!.4?5?5j*j:?V0V2:25:!4:?V!2fj2
R;BjwRjjcjjccjjjjjjccjjccjjccjjcjjjccjjN;
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RNH30DkbRol"Lng.
";N3HR#_klDOk0_bHMk.0R;H
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";N3HR#_klDOk0_bHMk.0R;H
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