代码搜索：FPGA EDK
找到约 10,000 项符合「FPGA EDK」的源代码
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www.eeworm.com/read/157781/11663141
txt readme_ddr_verilog.txt
README file: Virtex-II Platform FPGA Handbook
=============================================
Date: March, 2001
Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
www.eeworm.com/read/157780/11663189
txt readme_dcm_verilog.txt
README file: Virtex-II Platform FPGA Handbook
=============================================
Date: March, 2001
Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
www.eeworm.com/read/157778/11663282
txt readme_blockram_verilog.txt
README file: Virtex-II Platform FPGA Handbook
=============================================
Date: March, 2001
Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
www.eeworm.com/read/157209/11730154
txt 相应加法器的测试向量（test bench).txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/149607/12362912
vhd testadder.vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/227189/14437628
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/125701/14470247
vhd testadder.vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/17670/753467
lst netlist.lst
E:\linpingping\ATCA_converge_board\LVDS_Serdes_list_FPGA1\lvds_bist_top_cs.ngc 1231685755
OK
www.eeworm.com/read/17694/754290
lst netlist.lst
E:\linpingping\ATCA_converge_board\DAC\LVDS_DDR_List_FPGA2\DDR_TX_TEST.ngc 1234863246
OK
www.eeworm.com/read/457775/1593271
lst project.lst
0
F:\FPGA大赛\FUSION STARTKIT (G)\实验例程\高级实验\LCD实验\Project\LCD_1602\synthesis\viewdraw\ viewdraw