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-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D

// download from: www.pld.com.cn & www.fpga.com.cn module test_counter; reg clk, rst; wire [7:0] count; counter #(5,10) dut (count,clk,rst); initial // Clock generator begin cl

// User-Defined Macrofunction // download from: http://www.fpga.com.cn module reg12 ( d, clk, q); input [11:0]d; input clk; output [11:0]q; reg [11:0]q; always @(posedge clk)

Project Information d:\program\fpga\led driver\test_createspi.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 02/13/2009 16:11:50 Copyright (C) 1988-2002 Al

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INIT_FILE="e:\ywh\maxplus\fpga\sinwavegenerator\sin512.mif" NUMWORDS_A=512 OPERATION_MODE="ROM" OUTDATA

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INIT_FILE="e:\ywh\maxplus\fpga\sinwavegenerator\sin512.mif" NUMWORDS_A=512 OPERATION_MODE="ROM" OUTDATA

From: Subject: =?gb2312?B?RE05MDAwQdStwO28sMbk0+u7+bT40MW6xbSmwO3GvcyotcS94brP06bTwyw=?= =?gb2312?B?U0RSLERNOTAwMEEsRlBHQSzS1Myrzfgt1tC15834?= Date: Tue, 26 Au