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FPGA 的代码
fpga控制ad后led显示.v
module led1(mclk,led,da,clk_out);
input mclk;
output [3:0] led;
output clk_out;
reg [3:0] led;
reg [7:0] data;
input [7:0] da;
reg [2:0] count;
reg [2:0] state;
wire clk;
wire clk_out;
reg
uartctrl.h
#ifndef __UARTCTRL_H
#define __UARTCTRL_H
#define FPGA_UART_EN 1
/*
* 根据代码配置, 选择FPGA配置的UART或单片机内部UART
*/
#ifndef FPGA_UART_EN
#error Have not define the macro FPGA_UART_EN
#endif
#i
tcl_stacktrace.txt
Thu May 07 21:04:51 中国标准时间 2009
Trace back: ** Error: (vish-7) Failed to open mpf file "F:/EdaOk/project/PeriphDIY/uart/fpga/V0p00/testbench/uart.mpf" in write mode.
Permission denied. (errno = EACC
_info
m255
13
cModel Technology
dE:\Modeltech_6.2b\examples
vdivider
VSR;j5X`V3M@fU:::;KDza2
r1
31
IKc7D>k7lez?To?`h
_info
m255
13
cModel Technology
dF:\EdaOk\project\PeriphDIY\uart\fpga\V0p00\testbench
uart.cr.mti
F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v {2 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v
Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
读我.txt
“<mark>fpga</mark>”文件夹为<mark>FPGA</mark>的QuartusII工程文件，使用VerilogHDL语言，目标芯片为EP1C3T144C8
“MCU”文件夹为测试<mark>FPGA</mark>设计的单片机IAR工程文件，使用C语言，目标芯片为ATMEGA64L-8AU
“创造力电子开发网”文件夹是该创造力电子开发网网站（http://www.edaok.net/）的快捷方式。
“UART设计文档.pdf”文件是介绍使用 ...
fpga64_bustiming.vhd
-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA