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FPGA 的代码
tst_alu_2bit.vhw
-- G:\VIJAY_FPGA_LAB\ALU_2BIT
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Mar 09 14:22:39 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Te
alu_2bit.vhw
-- G:\VIJAY_FPGA_LAB\ALU_2BIT
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sat Feb 18 09:35:47 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Te
最高优先级编码器.txt
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
一个简单的状态机.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
加法器源程序.v
// download from: www.pld.com.cn & www.fpga.com.cn
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter
muluva16.v
//
// PROJECT: OpenDSP - The 'DSPuva16' 16-bit fixed-point DSP for FPGA
// http://www.DTE.eis.uva.es/OpenProjects/OpenDSP/index.htm
//
// RIGHTS: Santiago de Pablo
// Copyright (c) 2001. All Ri
aluuva16.v
//
// PROJECT: OpenDSP - The 'DSPuva16' 16-bit fixed-point DSP for FPGA
// http://www.DTE.eis.uva.es/OpenProjects/OpenDSP/index.htm
//
// RIGHTS: Santiago de Pablo
// Copyright (c) 2001. All Ri
dspuva16.v
//
// PROJECT: OpenDSP - The 'DSPuva16' 16-bit fixed-point DSP for FPGA
// http://www.DTE.eis.uva.es/OpenProjects/OpenDSP/index.htm
//
// RIGHTS: Santiago de Pablo
// Copyright (c) 2001. All Ri