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-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Wed Apr 12 15:09:04 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Wed Apr 12 14:53:31 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Fri Apr 07 09:31:34 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

-- D:\FPGA\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Tue Apr 25 15:07:50 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Bench Wa

/* * Cisco router simulation platform. * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) * * Cisco 7200 I/O FPGA: * - Simulates a NMC93C46 Serial EEPROM as CPU and Midplane EEPROM. * -

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in

-- Pelican Crossing Controller -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity pelcross is port(clock, reset, pedestrian : in std_logic;

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in