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/* Simulation model of Xilinx FPGA BlockRAM memory 2002 A.S.Slusarczyk@tue.nl */ #ifndef XLXRAM_H_INCLUDED #define XLXRAM_H_INCLUDED #include #include "mips.h" #ifndef VERILOG #inc

`include "timescale.v" //`define VENDOR_XILINX //`define VENDOR_ALTERA `define VENDOR_FPGA module generic_spram( // Generic synchronous single-port RAM interface clk, rst, ce, we, oe, ad

-- D:\FPGA\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Tue Apr 25 13:02:02 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Bench Wa

-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Tue Apr 11 13:47:18 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Mon Apr 10 09:01:43 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Thu Apr 06 15:41:45 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Thu Apr 06 17:11:47 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben

-- D:\FPGA\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Tue Apr 25 14:49:45 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Bench Wa

-- D:\FPGA\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Tue Apr 25 16:03:09 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Bench Wa

-- D:\FPGA\TEST\XC_9572 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Fri Apr 07 10:07:45 2006 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Ben