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【51电子网】-电子技术资料-宽频带数字锁相环的设计及基于fpga的实现.htm
【51电子网】-电子技术资料-宽频带数字锁相环的设
双向总线（注2）.txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
雙向總線(注2).txt
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
双向总线.vhd
VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn
bidir.vhd (Tri-state bus implementation)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
PORT(
bi
usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
sysproteus.h
/* sysProteus.h - Wind River PROTEUS FPGA board definitions */
/* Copyright 1984-2001 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,22nov01,g_h created.
*/
/*
DESCRI