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FPGA 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_a_cc is
generic(
adr_srbuf : integer := 48;
adr_swbuf : integer := 49;
adr_vrbuf_0 : integer := 16;
ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
stubi.vhd
-- Generated PORTMAP Stub File: Created by Capture FPGA Flow
-- Matches PCB component pinout with simulation model
-- Created Wednesday, May 13, 2009 08:10:07 中国标准时间
z80ip_t.v
//
// FPGA PACMAN Z80 interface for Daniel Wallner's T80
//
// Version : beta2
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freew
ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
led.v
// Light 8 LED
// Designed By Smokingfish @ www.51FPGA.com zhiyuh@163.com
module LED (LED);
output [13:0] LED;
assign LED=14'b11100110111001;//"CP"
endmodule
ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
verilog
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
ram_descramb.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = "D:\DLP\FPGA Projects\CellSearch03"
SET speedgrade = -12
SET simulationfiles = B
mssccprj.scc
[SCC]
SCC=This is a source code control file
[FPGA串行通讯.vbp]
SCC_Project_Name=this project is not under source code control
SCC_Aux_Path=