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readme.ml300

Xilinx ML300 platform ===================== 0. Introduction --------------- The Xilinx ML300 board is based on the Virtex-II Pro FPGA with integrated IBM PowerPC 405 core. The board is normally boot

test_dualport.ucf

# XSA Board FPGA pin assignment constraints NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %; # SDRAM memory tester pin assignments net

test_dualport.ucf

# XSA Board FPGA pin assignment constraints NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %; # SDRAM memory tester pin assignments net

test_dualport.ucf

# XSA Board FPGA pin assignment constraints NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %; # SDRAM memory tester pin assignments net

usx2yhwdep.c

/* * Driver for Tascam US-X2Y USB soundcards * * FPGA Loader + ALSA Startup * * Copyright (c) 2003 by Karsten Wiese * * This program is free software; you can redi

usx2yhwdep.c

/* * Driver for Tascam US-X2Y USB soundcards * * FPGA Loader + ALSA Startup * * Copyright (c) 2003 by Karsten Wiese * * This program is free software; you can redi

usx2yhwdep.c

/* * Driver for Tascam US-X2Y USB soundcards * * FPGA Loader + ALSA Startup * * Copyright (c) 2003 by Karsten Wiese * * This program is free software; you can redi

readme

rrc_complex =========== This module is used to interface the ICS-cards in a fast way. The operations done here should be put in the cards FPGA later. For the reception-part, two versions exist: one

readme

rrc_complex =========== This module is used to interface the ICS-cards in a fast way. The operations done here should be put in the cards FPGA later. For the reception-part, two versions exist: one

readme.ml300

Xilinx ML300 platform ===================== 0. Introduction --------------- The Xilinx ML300 board is based on the Virtex-II Pro FPGA with integrated AMCC PowerPC 405 core. The board is normally boo