test_dualport.ucf

xilinx 开发板原程序

# XSA Board FPGA pin assignment constraints

NET      "clk"     TNM_NET  =      "clk"; 
TIMESPEC "TS_clk"  =        PERIOD "clk"  10 ns HIGH 50 %; 

# SDRAM memory tester pin assignments
net      ce_n      loc=M15; # Flash RAM chip-enable
net      sw2       loc=E3;  # active-low pushbutton
net      clk       loc=R8;  # main 100 MHz clock
#net      clk       loc=B8;  # main  50 MHz clock
net      sclkfb    loc=N8;  # feedback SDRAM clock after PCB delays
net      sclk      loc=J4;  # clock to SDRAM
net      cke       loc=L1;  # SDRAM clock enable
net      cs_n      loc=J3;  # SDRAM chip-select
net      ras_n     loc=J2;  
net      cas_n     loc=H3;  
net      we_n      loc=G1;  
net      ba<0>     loc=K2;  
net      ba<1>     loc=L2;  
net      sAddr<0>  loc=L4;  
net      sAddr<1>  loc=N1;  
net      sAddr<2>  loc=N2;  
net      sAddr<3>  loc=M4;  
net      sAddr<4>  loc=T5;  
net      sAddr<5>  loc=N6;  
net      sAddr<6>  loc=M6;  
net      sAddr<7>  loc=T3;  
net      sAddr<8>  loc=N5;  
net      sAddr<9>  loc=P1;  
net      sAddr<10> loc=L3;  
net      sAddr<11> loc=M3;  
net      sAddr<12> loc=M2;  
net      sData<0>  loc=C2;  
net      sData<1>  loc=C1;  
net      sData<2>  loc=F5;  
net      sData<3>  loc=D1;  
net      sData<4>  loc=F3;  
net      sData<5>  loc=F2;  
net      sData<6>  loc=F1;  
net      sData<7>  loc=G3;  
net      sData<8>  loc=G4;  
net      sData<9>  loc=G5;  
net      sData<10> loc=E2;  
net      sData<11> loc=E4;  
net      sData<12> loc=B1;  
net      sData<13> loc=A2;  
net      sData<14> loc=D5;  
net      sData<15> loc=C5;  
net      dqmh      loc=H1;  
net      dqml      loc=G2;  
net      s<0>      loc=N14; 
net      s<1>      loc=D14; 
net      s<2>      loc=N16; 
net      s<3>      loc=M16; 
net      s<4>      loc=F15; 
net      s<5>      loc=J16; 
net      s<6>      loc=G16; 
net      pps<6>    loc=J13; 

INST "u0_fast_memtest_port0*" AREA_GROUP=memtest0;
INST "u0_fast_memtest_port1*" AREA_GROUP=memtest1;
INST "u0_u1*" AREA_GROUP=dualport;
INST "u0_u2_u1*" AREA_GROUP=sdramcntl;
AREA_GROUP "memtest0" RANGE=CLB_R1C10:CLB_R28C12;
AREA_GROUP "memtest1" RANGE=CLB_R1C10:CLB_R28C12;
AREA_GROUP "dualport" RANGE=CLB_R1C8:CLB_R28C9;
AREA_GROUP "sdramcntl" RANGE=CLB_R1C1:CLB_R28C7;