代码搜索结果

m255 cModel Technology de:\program\fpga_program\for_fpga\can\ise\canbus vcan_acf IV^L;BVT]]=4kB?3^f5iD^0 V7KkB[VcOEkYNUAC[hg:703 w1105406889 Fcan_acf.v Ftimescale.v Fcan_defines.v L0 83 OE;L;5.7e;17 r

m255 cModel Technology de:\program\fpga_program\for_fpga\can\ise\canbus vcan_acf IV^L;BVT]]=4kB?3^f5iD^0 V7KkB[VcOEkYNUAC[hg:703 w1105406889 Fcan_acf.v Ftimescale.v Fcan_defines.v L0 83 OE;L;5.7e;17 r

m255 cModel Technology de:\program\fpga_program\for_fpga\can\ise\canbus vcan_acf IV^L;BVT]]=4kB?3^f5iD^0 V7KkB[VcOEkYNUAC[hg:703 w1105406889 Fcan_acf.v Ftimescale.v Fcan_defines.v L0 83 OE;L;5.7e;17 r

礦ision3 Build Log Project: E:\YCL-USB2.0-FPGA开发板V2.0\测试程序源代码（包括VC工程文件及Firmware,Verilog代码）\USB2.0+FPGA_EXAMPLES\USB_GPIF_RW_SRAM测试\firmware\GPIF_fifo\firmware

m255 cModel Technology de:\program\fpga_program\for_fpga\can\ise\canbus vcan_acf IV^L;BVT]]=4kB?3^f5iD^0 V7KkB[VcOEkYNUAC[hg:703 w1105406889 Fcan_acf.v Ftimescale.v Fcan_defines.v L0 83 OE;L;5.7e;17 r

-- Modification by Koay Kah Hoe -- Optimize for Xilinx Spartan II FPGA implementation -- Version : 2.9a -- -- Copyright (c) 1999-2001 Tony Givargis. Permission to copy is granted -- provided that thi

-- -- Module: DECODE_4 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip

-- -- Module: DECODE_3 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip

-- -- Module: DECODE_1 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip

-- -- Module: DECODE_2 -- Design: CAM_Top -- VHDL code: RTL / Combinatorial -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attributes -- -- Descrip