i8051_ctr.vhd

8051 VHDL IP Core

-- Modification by Koay Kah Hoe
-- Optimize for Xilinx Spartan II FPGA implementation
-- Version : 2.9a
--
-- Copyright (c) 1999-2001 Tony Givargis.  Permission to copy is granted
-- provided that this header remains intact.  This software is provided
-- with no warranties.
--
-- Version : 2.9
--

-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;

-------------------------------------------------------------------------------

--
-- rst (active hi) : when asserted the controller state is reset
-- clk (rising edge) : clock signal
-- rom_addr : this is the rom address being requested
-- rom_data : this is the data returned by rom
-- rom_rd (active lo) : asserted to signal a rom read
-- ram_addr : this is the address of ram/reg being requested
-- ram_out_data : this is the data sent to the ram/reg
-- ram_in_data : this is the data received from the ram/reg
-- ram_out_bit_data : this is the bit-data sent to the ram/reg
-- ram_in_bit_data : this is the bit-data received from the ram/reg
-- ram_rd (active lo) : asserted to signal a ram/reg read
-- ram_wr (active lo) : asserted to signal a ram/reg write
-- ram_is_bit_addr (active hi) : asserted if requesting a ram/reg bit-data
-- xrm_addr : this is the address of external memory being requested
-- xrm_out_data : this is the data sent to the external memory
-- xrm_in_data : this is the data received from the external memory
-- xrm_rd (active lo) : asserted to signal a external memory read
-- xrm_wr (active lo) : asserted to signal a external memory write
-- dec_op_out : actual variable length opcode sent to decoder (see 8051 specs)
-- dec_op_in(6 downto 0) : cracked (fixed length) opcode (see I8051_LIB)
-- dec_op_in(7) : set if this instruction uses a second byte of data
-- dec_op_in(8) : set if this instruction uses a third byte of data
-- alu_op_code : defines the alu operation requested (see I8051_LIB)
-- alu_src_1 : first source operand of the alu (see I8051_ALU)
-- alu_src_2 : second source operand of the alu (see I8051_ALU)
-- alu_src_3 : third source operand of the alu (see I8051_ALU)
-- alu_src_cy : carry into the 7th bit of the alu (see I8051_ALU)
-- alu_src_ac : carry into the 4th bit of the alu (see I8051_ALU)
-- alu_des_1 : first destination operand of the alu (see I8051_ALU)
-- alu_des_2 : second destination operand of the alu (see I8051_ALU)
-- alu_des_cy : carry out of the 7th bit of the alu (see I8051_ALU)
-- alu_des_ac : carry out of the 4th bit of the alu (see I8051_ALU)
-- alu_des_ov : overflow out of the alu (see I8051_ALU)
--
entity I8051_CTR is
	port (rst              : in  STD_LOGIC;
         clk              : in  STD_LOGIC;
         rom_addr         : out UNSIGNED (11 downto 0);
         rom_data         : in  UNSIGNED (7 downto 0);
         rom_rd           : out STD_LOGIC;
         ram_addr         : out UNSIGNED (7 downto 0);
         ram_out_data     : out UNSIGNED (7 downto 0);
         ram_in_data      : in  UNSIGNED (7 downto 0);
         ram_out_bit_data : out STD_LOGIC;
         ram_in_bit_data  : in  STD_LOGIC;
         ram_rd           : out STD_LOGIC;
         ram_wr           : out STD_LOGIC;
         ram_is_bit_addr  : out STD_LOGIC;
         xrm_addr         : out UNSIGNED (15 downto 0);
         xrm_out_data     : out UNSIGNED (7 downto 0);
         xrm_in_data      : in  UNSIGNED (7 downto 0);
         xrm_rd           : out STD_LOGIC;
         xrm_wr           : out STD_LOGIC;
         dec_op_out       : out UNSIGNED (7 downto 0);
         dec_op_in        : in  UNSIGNED (8 downto 0);
         alu_op_code      : out UNSIGNED (3 downto 0);
         alu_src_1        : out UNSIGNED (7 downto 0);
         alu_src_2        : out UNSIGNED (7 downto 0);
         alu_src_3        : out UNSIGNED (7 downto 0);
         alu_src_cy       : out STD_LOGIC;
         alu_src_ac       : out STD_LOGIC;
         alu_des_1        : in  UNSIGNED (7 downto 0);
         alu_des_2        : in  UNSIGNED (7 downto 0);
         alu_des_cy       : in  STD_LOGIC;
         alu_des_ac       : in  STD_LOGIC;
         alu_des_ov       : in  STD_LOGIC
	);
end I8051_CTR;

architecture BHV of I8051_CTR is

    type CPU_STATE_TYPE is (CS_0, CS_1, CS_2, CS_3);
    type EXE_STATE_TYPE is (ES_0, ES_1, ES_2, ES_3, ES_4, ES_5, ES_6, ES_7);
    
    signal reg_pc_15_11 : UNSIGNED (4 downto 0);
    signal reg_pc_10_8  : UNSIGNED (2 downto 0);
    signal reg_pc_7_0   : UNSIGNED (7 downto 0);
    signal reg_op1      : UNSIGNED (7 downto 0);
    signal reg_op2      : UNSIGNED (7 downto 0);
    signal reg_op3      : UNSIGNED (7 downto 0);
    signal reg_acc      : UNSIGNED (7 downto 0);
    signal reg_cy       : STD_LOGIC;
    signal reg_ac       : STD_LOGIC;
    signal reg_f0       : STD_LOGIC;
    signal reg_rs1      : STD_LOGIC;
    signal reg_rs0      : STD_LOGIC;
    signal reg_ov       : STD_LOGIC;
    signal reg_nu       : STD_LOGIC;
    signal reg_p        : STD_LOGIC;

    signal cpu_state : CPU_STATE_TYPE;
    signal exe_state : EXE_STATE_TYPE;

begin

    process(rst, clk)

-------------------------------------------------------------------------------

        procedure SET_PC_1 (pch, pcl : UNSIGNED (7 downto 0)) is
        begin
            reg_pc_15_11 <= pch(7 downto 3);
            reg_pc_10_8 <= pch(2 downto 0);
            reg_pc_7_0 <= pcl;
        end SET_PC_1;

-------------------------------------------------------------------------------

        procedure SET_PC_2 (pch : UNSIGNED (2 downto 0);
                            pcl : UNSIGNED (7 downto 0)) is
        begin
            reg_pc_10_8 <= pch;
            reg_pc_7_0 <= pcl;
        end SET_PC_2;
        
-------------------------------------------------------------------------------

        procedure SET_PC_H (pch : UNSIGNED (7 downto 0)) is
        begin
            reg_pc_15_11 <= pch(7 downto 3);
            reg_pc_10_8 <= pch(2 downto 0);
        end SET_PC_H;
        
-------------------------------------------------------------------------------

        procedure SET_PC_L (pcl : UNSIGNED (7 downto 0)) is
        begin
            reg_pc_7_0 <= pcl;
        end SET_PC_L;
        
-------------------------------------------------------------------------------

        procedure GET_PC_H (pch : out UNSIGNED (7 downto 0)) is
        begin
            pch := reg_pc_15_11 & reg_pc_10_8;
        end GET_PC_H;
        
-------------------------------------------------------------------------------

        procedure GET_PC_L (pcl : out UNSIGNED (7 downto 0)) is
        begin
            pcl := reg_pc_7_0;
        end GET_PC_L;
        
-------------------------------------------------------------------------------
        
        procedure GET_RAM_ADDR_1 (a : out UNSIGNED (7 downto 0)) is
        begin
            a := "000" & reg_rs1 & reg_rs0 & reg_op1(2 downto 0);
        end GET_RAM_ADDR_1;

-------------------------------------------------------------------------------
        
        procedure GET_RAM_ADDR_2 (a : out UNSIGNED (7 downto 0)) is
        begin
            a := "000" & reg_rs1 & reg_rs0 & "00" & reg_op1(0);
        end GET_RAM_ADDR_2;

-------------------------------------------------------------------------------

        procedure SET_PSW (p : UNSIGNED (7 downto 0)) is
        begin
            reg_cy <= p(7);
            reg_ac <= p(6);
            reg_f0 <= p(5);
            reg_rs1 <= p(4);
            reg_rs0 <= p(3);
            reg_ov <= p(2);
            reg_nu <= p(1);
            reg_p <= p(0);
        end SET_PSW;
        
-------------------------------------------------------------------------------

        procedure GET_PSW (p : out UNSIGNED (7 downto 0)) is
        begin
            p(7) := reg_cy;
            p(6) := reg_ac;
            p(5) := reg_f0;
            p(4) := reg_rs1;
            p(3) := reg_rs0;
            p(2) := reg_ov;
            p(1) := reg_nu;
            p(0) := reg_p;
        end GET_PSW;
        
-------------------------------------------------------------------------------

        procedure START_RD_ROM (h, l : UNSIGNED (7 downto 0)) is
        begin
            rom_addr <= h(3 downto 0) & l;
            rom_rd <= '1';
        end START_RD_ROM;

-------------------------------------------------------------------------------
        
        procedure STOP_RD_ROM is
        begin
            rom_addr <= CD_12;
            rom_rd <= '0';
        end STOP_RD_ROM;

-------------------------------------------------------------------------------

        procedure START_RD_RAM (a : UNSIGNED (7 downto 0)) is
        begin
            ram_addr <= a;
            ram_is_bit_addr <= '0';
            ram_rd <= '1';
            ram_wr <= '0';
        end START_RD_RAM;

-------------------------------------------------------------------------------
        
        procedure START_WR_RAM (a : UNSIGNED (7 downto 0)) is
        begin
            ram_addr <= a;
            ram_is_bit_addr <= '0';
            ram_rd <= '0';
            ram_wr <= '1';
        end START_WR_RAM;

-------------------------------------------------------------------------------
        
        procedure START_RD_BIT_RAM (a : UNSIGNED (7 downto 0)) is
        begin
            ram_addr <= a;
            ram_is_bit_addr <= '1';
            ram_rd <= '1';
            ram_wr <= '0';
        end START_RD_BIT_RAM;

-------------------------------------------------------------------------------
        
        procedure START_WR_BIT_RAM (a : UNSIGNED (7 downto 0)) is
        begin
            ram_addr <= a;
            ram_is_bit_addr <= '1';
            ram_rd <= '0';
            ram_wr <= '1';
        end START_WR_BIT_RAM;

-------------------------------------------------------------------------------
        
        procedure STOP_RD_WR_RAM is
        begin
            ram_addr <= CD_8;
            ram_out_data <= CD_8;
            ram_out_bit_data <= '-';
            ram_is_bit_addr <= '-';
            ram_rd <= '0';
            ram_wr <= '0';
        end STOP_RD_WR_RAM;

-------------------------------------------------------------------------------

        procedure START_RD_XRM (a : UNSIGNED (15 downto 0)) is
        begin
            xrm_addr <= a;
            xrm_rd <= '1';
            xrm_wr <= '0';
        end START_RD_XRM;

-------------------------------------------------------------------------------
        
        procedure START_WR_XRM (a : UNSIGNED (15 downto 0)) is
        begin
            xrm_addr <= a;
            xrm_rd <= '0';
            xrm_wr <= '1';
        end START_WR_XRM;

-------------------------------------------------------------------------------
        
        procedure STOP_RD_WR_XRM is
        begin
            xrm_addr <= CD_16;
            xrm_out_data <= CD_8;
            xrm_rd <= '0';
            xrm_wr <= '0';
        end STOP_RD_WR_XRM;

-------------------------------------------------------------------------------

        procedure SHUT_DOWN_ALU is
        begin
            alu_op_code <= ALU_OPC_NONE;
            alu_src_1 <= CD_8;
            alu_src_2 <= CD_8;
            alu_src_3 <= CD_8;
            alu_src_cy <= '-';
            alu_src_ac <= '-';
        end SHUT_DOWN_ALU;

-------------------------------------------------------------------------------

        variable v8, pcl, pch  : UNSIGNED (7 downto 0);
    begin
        
        if( rst = '1' ) then

            SET_PC_1(C0_8, C0_8);
            
            reg_op1 <= C0_8;
            reg_op2 <= CD_8;
            reg_op3 <= CD_8;
            reg_acc <= CD_8;

            SET_PSW(C0_8);
            
            cpu_state <= CS_0;
            exe_state <= ES_0;

            STOP_RD_ROM;