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FPGA 的代码
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
usbotg_internal.h
/********** Macro definition for SW level**********************************/
//#define PRINT
//#define Tahiti
//#define FPGA
//#define NOLM
//#define UartTest //Uart test only (5 polling times)
wed.zsf
D:/整理资料/fpga/分频器/db/clkdiv.sim.vwf 6368812 11642352 390 5273540 0
D:/整理资料/fpga/分频器/clkdiv.vwf 102713432 106619682 597 3906250 0
clkdiv.vwf 0 1000000000 20 1000 0
C:/desk/f/db/clkdiv.sim.vwf 0 14827
top.bld
Release 6.2i - ngdbuild G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd
e:\lqj\sram+fpga+usb\读sram\ram-usb\fpga/_ngo -uc ucf.ucf -p xc3s400-p
myosctest_modelsim.xrf
vendor_name = ModelSim
source_file = 1, C:/franchiese/FPGA文档资料/altera设计实例/MAX II和MAX设计实例/an496_design_example/myosctest/myosctest.v
source_file = 1, C:/franchiese/FPGA文档资料/altera设计实例/MAX II和MAX设计实例/
wed.zsf
D:/整理资料/fpga/分频器/db/clkdiv.sim.vwf 6368812 11642352 390 5273540 0
D:/整理资料/fpga/分频器/clkdiv.vwf 102713432 106619682 597 3906250 0
clkdiv.vwf 0 1000000000 20 1000 0
C:/desk/f/db/clkdiv.sim.vwf 0 14827
lcd_top_syn.prj
#add_file options
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project
lcd_top_syn.prj.convert.sav
#add_file options
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "F:/FPGA大赛/FUSION STARTKIT (G)/实验例程/高级实验/LCD实验/Project
isim.hdlsourcefiles
C:/Xilinx/ISE81/verilog/src/glbl.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/verilog/lab6/kcuart_rx.v
C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/lab
isim.hdlsourcefiles
C:/Xilinx/ISE82/verilog/src/glbl.v
C:/XUP/Markets/PLDs/Workshops/courses/v82_fpga_flow/xupv2pro/labsolutions/verilog/lab5/kcuart_rx.v
C:/XUP/Markets/PLDs/Workshops/courses/v82_fpga_flow/xupv2pro/lab