代码搜索结果

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -ifn E:/linpingping/ATCA_converge_board/DAC/L

E:\※※※硬件描述语言与数字系统设计\※※※本科教学—硬件描述语言与数字系统设计\※※※郑朝霞-上课讲义\PPT\FPGA设计实例\ps2\ISE\PS2\fpga_40Aps2.ngc 1206967790 OK

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v source_file

{E:/farsight_fpga_course/code/high/onchip ram/test/simulation/modelsim/ram_top.v} {1 {vlog -work work1 -vlog01compat {E:/farsight_fpga_course/code/high/onchip ram/test/simulation/modelsim/ram_top.v}

CommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise E:/pham thanh cong/My Documents/Bai FPGA/AD7823/AD7823.ise -intstyle ise -ifn E:/pham thanh cong/My Documents/Bai FPGA/AD7823/ADCcontroller

Project Informationf:\work\fpga_platform\fpga_evm\20041113\lcd_max\lcd_max_wrapper\lcd.rpt MAX+plus II Compiler Report File Version 10.0 9/14/2000 Compiled: 12/06/2004 22:15:21 Copyright (C) 1

EN usbtest NULL D:/usb/FPGA_CPLD/USB_TEST/usbtest.vhd sub00/vhpl00 1220499205 AR usbtest behavioral D:/usb/FPGA_CPLD/USB_TEST/usbtest.vhd sub00/vhpl01 1220499206

基于FPGA的VHDL时钟程序 本程序是基于FPGA的时钟程序,可用按键控制较时,有秒闪,调时指示!!! library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ---------------------------------------------- e

D:/整理资料/fpga/分频器1/db/div2.sim.vwf 0 64000000 390 64000000 0 D:/整理资料/fpga/分频器1/div2.vwf 0 1000000 20 1000 0 div2.vwf 0 0 0 0 0 D:/整理资料/fpga/分频器的设计/分频器1/db/div2.sim.vwf 46366409 77616409 553 31250000

m255 cModel Technology dF:\FPGA_LMS Ecosfunc DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2 w1120917906 dF:\FPGA_LMS4\FPGA_LMS3 Fcosfunc.vhd l0 L43 V@Z?[8Rm3B3UXSVlDVAK=g2 OE;C;5.8c;15 31 o-93 -explici