代码搜索结果

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v

CommandLine-Map s CommandLine-Ngdbuild E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -dd _ngo -nt time

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -ifn E:/linpingping/ATCA_converge_board/LVDS_Serde

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\stratix.v,

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v

Synthesizing work.armexio.armexio @W:"E:\Exp23_1\FPGA\armExIO.vhd":84:7:84:13|Incomplete sensitivity list - assuming completeness @W:"E:\Exp23_1\FPGA\armExIO.vhd":89:25:89:28|Referenced variable dat

/README/1.1.1.1/Sun May 30 09:42:44 2004//D2004.05.31.16.00.00 /fpga.c/1.1.1.1/Sun May 30 09:42:44 2004//D2004.05.31.16.00.00 /fpga.h/1.1.1.1/Sun May 30 09:42:44 2004//D2004.05.31.16.00.00 D