armexio.tlg

usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全部源代码分别存放在各实验目录下面。

Synthesizing work.armexio.armexio
@W:"E:\Exp23_1\FPGA\armExIO.vhd":84:7:84:13|Incomplete sensitivity list - assuming completeness
@W:"E:\Exp23_1\FPGA\armExIO.vhd":89:25:89:28|Referenced variable data is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":87:8:87:14|Referenced variable address is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":111:6:111:12|Incomplete sensitivity list - assuming completeness
@W:"E:\Exp23_1\FPGA\armExIO.vhd":130:22:130:25|Referenced variable cnt4 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":122:11:122:14|Referenced variable iop2 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":118:11:118:14|Referenced variable iop1 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":126:11:126:14|Referenced variable iop3 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":116:8:116:14|Referenced variable address is not in sensitivity list
Post processing for work.armexio.armexio
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(36) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(32) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(33) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(34) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(35) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(36) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop1(36 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(35) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(34) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(33) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(32) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(31), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(30), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(29), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(28), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(27), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(26), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(25), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(25), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(24), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(24), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(23), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(23), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(22), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(22), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(21), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(21), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(20), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(20), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(19), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(19), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(18), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(18), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(17), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(17), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(16), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(16), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(15), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(15), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(14), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(14), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(13), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(13), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(12), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(12), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(11), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(11), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(10), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(10), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(9), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(9), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(8), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(8), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(7), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(7), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(6), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(6), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(5), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(5), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(4), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(4), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(3), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(3), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(2), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(2), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(1), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(1), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal cnt4(7 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":26:3:26:7|Input reset is unused
@W:"E:\Exp23_1\FPGA\armExIO.vhd":28:3:28:8|Input switch is unused
@W:"E:\Exp23_1\FPGA\armExIO.vhd":29:3:29:8|Input unused is unused