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# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

-- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

/* Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EP2C8Q208) Path("D:/altera/71/jiangbi

module frequency(RD,WR,ad,lk,hk,CS,A,clk,freq,ALE,aout,int,clear); input freq,clear,clk,RD,WR,ALE; input [15:13] A; input [4:1] hk; inout [7:0] ad; output [4:1] lk; outpu

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use std.textio.all; use work.pack.all; entity tb_sppe is end tb_sppe; archit

Type=Exe Form=主窗口.frm Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#C:\WIN98\SYSTEM\STDOLE2.TLB#OLE Automation Object={648A5603-2C6E-101B-82B6-000000000014}#1.1#0; MSCOMM32.OCX Object=

主窗口 = 44, 58, 869, 539, Z, 23, 23, 561, 472, C

verilog ../../../syn/src/verilog/oc8051_fpga_top.v ../../../bench/verilog/oc8051_fpga_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_