代码搜索结果

Output: EDIF for PCB Type : EDIF From : Project [FPGA_Counter.PrjFpg] Generated File[FPGA_Counter.EDF] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 23:47:

f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\rs232\ise\rs23240x\fpga_40RS232.ngc 1140944002 OK

f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\rs232\ise\rs23240x\fpga_40RS232.ngc 1140944002 OK

f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\rs232\ise\rs23240x\fpga_40RS232.ngc 1140944002 OK

礦ision2 Build Log Project: D:\FPGA\FPGA&USB\fifo_FPGA\FX2_to_extsyncFIFO.uv2 Project File Date: 03/12/2008 Output:

AR nor8_mxilinx_sx behavioral E:/Application/SJ/FPGA/SX.vhf sub00/vhpl05 1215655324 AR fifo fifo_a E:/Application/SJ/FPGA/FIFO.vhd sub00/vhpl03 1215655322 AR sx behavioral E:/Application/SJ/FPGA/SX.

############################################################################ ## This system.ucf file is generated by Base System Builder based on the ## settings in the selected Xilinx Board Definit

/* * arch/ppc/platforms/4xx/yucca.h * * Yucca board definitions * * Roland Dreier (based on luan.h by Matt Porter) * * Copyright 2004-2005 MontaVista Software Inc. * Copyri

# Xilinx CORE Generator 6.2.03i # Username = Chao.SEU # COREGenPath = C:\Xilinx\coregen # ProjectPath = F:\FPGA_LMS # ExpandedProjectPath = F:\FPGA_LMS # OverwriteFiles = true # Core name: multi

# Xilinx CORE Generator 6.2.03i # Username = Chao.SEU # COREGenPath = C:\Xilinx\coregen # ProjectPath = F:\FPGA_LMS # ExpandedProjectPath = F:\FPGA_LMS # OverwriteFiles = true # Core name: multi