system.ucf

working with powerpc in edk 9.2

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AE14;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=D6;
Net sys_rst_pin PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;

## IO Devices constraints

#### Module RS232_Uart constraints

Net fpga_0_RS232_Uart_RX_pin LOC=W2;
Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_Uart_TX_pin LOC=W1;
Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;

#### Module DDR_SDRAM constraints

Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=C26;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=E17;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=D18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=C19;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=F17;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=B18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=B20;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=C20;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=D20;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=C21;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=A18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=B21;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=A24;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=B12;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=A16;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=F23;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=G22;
Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=G21;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=F24;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=A23;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=G19;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=G24;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> LOC=G20;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> LOC=C22;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=D25;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=G18;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<2> LOC=G17;
Net fpga_0_DDR_SDRAM_DDR_DQS<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<3> LOC=D26;
Net fpga_0_DDR_SDRAM_DDR_DQS<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=H20;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=E23;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=H26;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=H22;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=E25;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=E26;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=F26;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=E24;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=E20;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=A22;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=C23;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=C24;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=A20;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=A21;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=D24;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=E18;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<16> LOC=F18;
Net fpga_0_DDR_SDRAM_DDR_DQ<16> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<17> LOC=A19;
Net fpga_0_DDR_SDRAM_DDR_DQ<17> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<18> LOC=F19;
Net fpga_0_DDR_SDRAM_DDR_DQ<18> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<19> LOC=B23;
Net fpga_0_DDR_SDRAM_DDR_DQ<19> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<20> LOC=E21;
Net fpga_0_DDR_SDRAM_DDR_DQ<20> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<21> LOC=D22;
Net fpga_0_DDR_SDRAM_DDR_DQ<21> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<22> LOC=D23;
Net fpga_0_DDR_SDRAM_DDR_DQ<22> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<23> LOC=B24;
Net fpga_0_DDR_SDRAM_DDR_DQ<23> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<24> LOC=E22;
Net fpga_0_DDR_SDRAM_DDR_DQ<24> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<25> LOC=F20;
Net fpga_0_DDR_SDRAM_DDR_DQ<25> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<26> LOC=H23;
Net fpga_0_DDR_SDRAM_DDR_DQ<26> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<27> LOC=G25;
Net fpga_0_DDR_SDRAM_DDR_DQ<27> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<28> LOC=G26;
Net fpga_0_DDR_SDRAM_DDR_DQ<28> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<29> LOC=H25;
Net fpga_0_DDR_SDRAM_DDR_DQ<29> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<30> LOC=H24;
Net fpga_0_DDR_SDRAM_DDR_DQ<30> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<31> LOC=H21;
Net fpga_0_DDR_SDRAM_DDR_DQ<31> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=A10;
Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = DIFF_SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=B10;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = DIFF_SSTL2_II;