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FPGA 的代码
ebony.c
/*
* $Id: ebony.c,v 1.16 2005/11/07 11:14:26 gleixner Exp $
*
* Mapping for Ebony user flash
*
* Matt Porter
*
* Copyright 2002-2004 MontaVista Software Inc.
*
*
ebony.c
/*
* $Id: ebony.c,v 1.1.1.1 2007/09/01 10:29:10 hansorblue Exp $
*
* Mapping for Ebony user flash
*
* Matt Porter
*
* Copyright 2002-2004 MontaVista Software Inc.
appnote_zbtp.v
/******************************************************************************
*
* Author: Shekhar Bapat
* Email: shekhar.bapat@xilinx.com
* Phone: (408) 879-5368
* Compan
fw_top.ucf
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
Net "fpga_0_RS232_Uart_1_RX_pin" LOC=AJ8;
Net "fpga_0_RS232_Uart_1_RX_pin" IOSTANDARD = LVCMOS25;
NET "fpga
buffer_comp_chrom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
q_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_img.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
tabla_q.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
huff_rom.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#