fw_top.ucf

本系统由服务器软件控制平台和fpga硬件处理系统组成

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
Net "fpga_0_RS232_Uart_1_RX_pin" LOC=AJ8;
Net "fpga_0_RS232_Uart_1_RX_pin" IOSTANDARD = LVCMOS25;
NET "fpga_0_RS232_Uart_1_TX_pin"  LOC = "AE7" | IOSTANDARD = LVCMOS25  | DRIVE = 12 ;
NET "MAC_PHY_rst_n"  LOC = "G6" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ; 
NET "MAC_slew1"  LOC = "B3" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ; 
NET "MAC_slew2"  LOC = "A3" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ; 
NET "sys_clk_in_100m"  LOC = "AJ15" | IOSTANDARD = LVCMOS25 ; 
NET "sys_rst_n_in"  LOC = "AH5" | IOSTANDARD = LVTTL ; 

Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[0]" LOC=AC4;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[0]" IOSTANDARD = LVTTL;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[0]" SLEW = SLOW;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[0]" DRIVE = 12;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[1]" LOC=AC3;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[1]" IOSTANDARD = LVTTL;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[1]" SLEW = SLOW;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[1]" DRIVE = 12;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[2]" LOC=AA6;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[2]" IOSTANDARD = LVTTL;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[2]" SLEW = SLOW;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[2]" DRIVE = 12;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[3]" LOC=AA5;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[3]" IOSTANDARD = LVTTL;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[3]" SLEW = SLOW;
Net "fpga_0_LEDs_4Bit_GPIO_IO_pin[3]" DRIVE = 12;

Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[0]" LOC=AC11;
Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[0]" IOSTANDARD = LVCMOS25;
Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[1]" LOC=AD11;
Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[1]" IOSTANDARD = LVCMOS25;
Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[2]" LOC=AF8;
Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[2]" IOSTANDARD = LVCMOS25;
Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[3]" LOC=AF9;
Net "fpga_0_DIPSWs_4Bit_GPIO_IO_pin[3]" IOSTANDARD = LVCMOS25;


Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[0]" LOC=AG5;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[0]" IOSTANDARD = LVTTL;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[1]" LOC=AH4;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[1]" IOSTANDARD = LVTTL;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[2]" LOC=AG3;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[2]" IOSTANDARD = LVTTL;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[3]" LOC=AH1;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[3]" IOSTANDARD = LVTTL;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[4]" LOC=AH2;
Net "fpga_0_PushButtons_5Bit_GPIO_IO_pin[4]" IOSTANDARD = LVTTL;

                                                                        
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin" LOC=AG2;              
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin" IOSTANDARD = LVTTL;   
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin" SLEW = SLOW;          
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin" DRIVE = 8;            
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin" LOC=AG1;             
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin" IOSTANDARD = LVTTL;  
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin" SLEW = SLOW;         
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin" DRIVE = 8;           
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin" LOC=AD6;               
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin" IOSTANDARD = LVTTL;    
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin" SLEW = SLOW;           
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin" DRIVE = 8;             
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin" LOC=AD5;              
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin" IOSTANDARD = LVTTL;   
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin" SLEW = SLOW;          
Net "fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin" DRIVE = 8;            


Net "fpga_0_net_gnd_pin" LOC=G12;
Net "fpga_0_net_gnd_pin" IOSTANDARD = LVTTL;
Net "fpga_0_net_gnd_pin" SLEW = SLOW;
Net "fpga_0_net_gnd_pin" DRIVE = 6;
Net "fpga_0_net_gnd_1_pin" LOC=D15;
Net "fpga_0_net_gnd_1_pin" IOSTANDARD = LVTTL;
Net "fpga_0_net_gnd_1_pin" SLEW = SLOW;
Net "fpga_0_net_gnd_1_pin" DRIVE = 6;
Net "fpga_0_net_gnd_2_pin" LOC=E15;
Net "fpga_0_net_gnd_2_pin" IOSTANDARD = LVTTL;
Net "fpga_0_net_gnd_2_pin" SLEW = SLOW;
Net "fpga_0_net_gnd_2_pin" DRIVE = 6;
Net "fpga_0_net_gnd_3_pin" LOC=G10;
Net "fpga_0_net_gnd_3_pin" IOSTANDARD = LVTTL;
Net "fpga_0_net_gnd_3_pin" SLEW = SLOW;
Net "fpga_0_net_gnd_3_pin" DRIVE = 6;
Net "fpga_0_net_gnd_4_pin" LOC=E10;
Net "fpga_0_net_gnd_4_pin" IOSTANDARD = LVTTL;
Net "fpga_0_net_gnd_4_pin" SLEW = SLOW;
Net "fpga_0_net_gnd_4_pin" DRIVE = 6;
Net "fpga_0_net_gnd_5_pin" LOC=G8;
Net "fpga_0_net_gnd_5_pin" IOSTANDARD = LVTTL;
Net "fpga_0_net_gnd_5_pin" SLEW = SLOW;
Net "fpga_0_net_gnd_5_pin" DRIVE = 6;
Net "fpga_0_net_gnd_6_pin" LOC=H9;
Net "fpga_0_net_gnd_6_pin" IOSTANDARD = LVTTL;
Net "fpga_0_net_gnd_6_pin" SLEW = SLOW;
Net "fpga_0_net_gnd_6_pin" DRIVE = 6;

NET "gmii_col"  LOC = "D5" | IOSTANDARD = LVTTL ; 
NET "gmii_crs"  LOC = "C5" | IOSTANDARD = LVTTL ; 
NET "gmii_rx_clk"  LOC = "M8" | IOSTANDARD = LVTTL ; 
NET "gmii_rx_dv"  LOC = "M7" | IOSTANDARD = LVTTL ; 
NET "gmii_rx_er"  LOC = "J2" | IOSTANDARD = LVTTL ; 
NET "gmii_rxd[0]"  LOC = "K6" | IOSTANDARD = LVTTL ; 
NET "gmii_rxd[1]"  LOC = "K5" | IOSTANDARD = LVTTL ; 
NET "gmii_rxd[2]"  LOC = "J1" | IOSTANDARD = LVTTL ; 
NET "gmii_rxd[3]"  LOC = "K1" | IOSTANDARD = LVTTL ; 
NET "gmii_tx_clk"  LOC = "D3" | IOSTANDARD = LVTTL ; 
NET "gmii_tx_en"  LOC = "C4" | IOSTANDARD = LVTTL  | SLEW = SLOW  | DRIVE = 8 ; 
NET "gmii_tx_er"  LOC = "H2" | IOSTANDARD = LVTTL ; 
NET "gmii_txd[0]"  LOC = "J7" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ; 
NET "gmii_txd[1]"  LOC = "J8" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ; 
NET "gmii_txd[2]"  LOC = "C1" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ; 
NET "gmii_txd[3]"  LOC = "C2" | IOSTANDARD = LVTTL  | DRIVE = 8  | SLEW = SLOW ; 

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE