代码搜索：FPGA

找到约 10,000 项符合「FPGA」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/300257/13924005

c c6711_dsk.c

/***************************************************************************** * File name : C6711_DSK.c * Description: *************************************************************************
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www.eeworm.com/read/235221/14081055

bak fpgadram.bak

#include #include unsigned int xdata start_addr; unsigned int xdata end_addr; unsigned int xdata address; unsigned int xdata data_address=0xa080; //双口RAM数据存放地址计数器 unsig
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www.eeworm.com/read/201251/15411985

cmd_log ddr_cntl_a.cmd_log

xst -ise "E:/hardware/KDVM26402/fpga/ddr_cntl_a_withtb/ddr_cntl_a_withtb" -intstyle ise -ifn ddr_cntl_a.xst -ofn ddr_cntl_a.syr ngdbuild -ise "E:/hardware/KDVM26402/fpga/ddr_cntl_a_withtb/ddr_cntl_a_
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www.eeworm.com/read/201251/15412028

v ddr_cntl_a_ddr1_test_bench_0.v

////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2005 Xilinx, Inc. // This design is confidential and proprietary of Xilinx, All Rights Reserved. ///////
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www.eeworm.com/read/201251/15412134

v ddr_cntl_a_ddr1_test_bench_0.v

////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2005 Xilinx, Inc. // This design is confidential and proprietary of Xilinx, All Rights Reserved. ///////
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www.eeworm.com/read/18537/793315

vhd cpld.vhd

--fpga FPP(fast passive parallel) configuration --fpga_conf_done in ：The FPGA will release the pin high when configuration is successful.配置成功后置高 --fpga_nstatus in ：FPGA pulls the pin low if a con
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www.eeworm.com/read/325655/3481124

gfl rs23240x.gfl

# XST (Creating Lso File) : fpga_40RS232.lso # xst flow : RunXST fpga_40RS232.syr fpga_40RS232.prj fpga_40RS232.sprj fpga_40RS232.ana fpga_40RS232.stx fpga_40RS232.cmd_log fpga_40RS232.ngc
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www.eeworm.com/read/318858/3561663

gfl rs23240x.gfl

# XST (Creating Lso File) : fpga_40RS232.lso # xst flow : RunXST fpga_40RS232.syr fpga_40RS232.prj fpga_40RS232.sprj fpga_40RS232.ana fpga_40RS232.stx fpga_40RS232.cmd_log fpga_40RS232.ngc
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www.eeworm.com/read/436752/1844998

gfl rs23240x.gfl

# XST (Creating Lso File) : fpga_40RS232.lso # xst flow : RunXST fpga_40RS232.syr fpga_40RS232.prj fpga_40RS232.sprj fpga_40RS232.ana fpga_40RS232.stx fpga_40RS232.cmd_log fpga_40RS232.ngc
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www.eeworm.com/read/18405/786500

kconfig

menu "AT91 FPGA" config AT91 FPGA bool "at91 fpga" default y endmenu
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