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FPGA 的代码
fpga_16bitcounter.prjfpgstructure
Record=TopLevelDocument|FileName=16Bit Counter.SchDoc
Record=Configuration|Name=EPM7128|DeviceName=EPM7128AELC84-10
fpga_16bitcounter.prjfpg
[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchivePr
fpga_16bitcounter.edf
(edif FPGA_16BitCounter_PrjFpg
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2010 5 8 10 29 5)
(program "Altium D
fpga_16bitcounter.edfpreview
[Preview]
LargeImageOriginalSize=708000
LargeImageWidth=354
LargeImageHeight=500
LargeImage=78DAEDDD0192E2489205D0B9591DADF7267D943ACA1CA57699316D7BFD720F09100924AFCC9E2509921064961319F115F1EBD7AF
fpga_16bitcounter.prjfpg
[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchivePr
fpga_project1.edfpreview
[Preview]
LargeImageOriginalSize=708000
LargeImageWidth=354
LargeImageHeight=500
LargeImage=78DAEDDD0B72DBC61205D0EC4C4BCBDB8997A2A578297A815313B7DADD03803F00D249D5295114097E1C354733173D1F1F1F7F7D
fpga_project1.edf
(edif FPGA_Project1_PrjFpg
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2010 5 27 16 1 39)
(program "Altium Desi
fpga_project1.prjfpg
[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchivePr
fpga_project1.prjfpgstructure
Record=TopLevelDocument|FileName=CPU.SchDoc
Record=Configuration|Name=EPM7128|DeviceName=EPM7128ELC84-20
fpga_project1.edfpreview
[Preview]
LargeImageOriginalSize=708000
LargeImageWidth=354
LargeImageHeight=500
LargeImage=78DAEDDD0B72DB48AF06D0ECCC4BCBBF932CC54BC952722F33D5098C004D524F523A5375CAB24C3D3D81DADD1FD1BF7EFDFAF60B