fpga_project1.prjfpg

altium designer09设计教程+原理图+PCB实例

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=1
PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1
VHDL87=0
Verilog95=0

[Document1]
DocumentPath=CPU.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=3
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document2]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\Pcb\Miscellaneous Connector PCB.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document3]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\Pcb\Miscellaneous Devices PCB.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document4]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\Texas Instruments\Texas Instruments Footprints.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document5]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\ON Semiconductor\ON Semi Logic Decoder Demux.IntLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document6]
DocumentPath=NB1_6_EPM7128ELC84.Constraint
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document7]
DocumentPath=Schlib1.SchLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document8]
DocumentPath=Test_fpga_project1.VHDTST
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[GeneratedDocument1]
DocumentPath=ProjectOutputs\CPU.VHD

[GeneratedDocument2]
DocumentPath=ProjectOutputs\FPGA_Project1.EDF

[Configuration1]
Name=EPM7128
ParameterCount=0
ConstraintFileCount=1
ConstraintFilePath1=NB1_6_EPM7128ELC84.Constraint

[OutputGroup1]
Name=Netlist Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=CadnetixNetlist
OutputName1=Cadnetix Netlist
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=CalayNetlist
OutputName2=Calay Netlist
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=EDIF
OutputName3=EDIF for PCB
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
Configuration3_Name1=OutputConfigurationParameter1
Configuration3_Item1=NetlistVersion=0|Record=EdifView
OutputType4=EESofNetlist
OutputName4=EESof Netlist
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=IntergraphNetlist
OutputName5=Intergraph Netlist
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
OutputType6=MentorBoardStationNetlist
OutputName6=Mentor BoardStation Netlist
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=MultiWire
OutputName7=MultiWire
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=OrCadPCB2Netlist
OutputName8=Orcad/PCB2 Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=PADSNetlist
OutputName9=PADS ASCII Netlist
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=Pcad
OutputName10=Pcad for PCB
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=PCADNetlist
OutputName11=PCAD Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=PCADnltNetlist
OutputName12=PCADnlt Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Protel2Netlist
OutputName13=Protel2 Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=ProtelNetlist
OutputName14=Protel
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=RacalNetlist
OutputName15=Racal Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=RINFNetlist
OutputName16=RINF Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=SciCardsNetlist
OutputName17=SciCards Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=SIMetrixNetlist
OutputName18=SIMetrix
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=SIMPLISNetlist
OutputName19=SIMPLIS
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=TangoNetlist
OutputName20=Tango Netlist
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=TelesisNetlist
OutputName21=Telesis Netlist
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=Verilog
OutputName22=Verilog File
OutputDocumentPath22=
OutputVariantName22=
OutputDefault22=0
OutputType23=VHDL
OutputName23=VHDL File
OutputDocumentPath23=
OutputVariantName23=
OutputDefault23=0
Configuration23_Name1=OutputConfigurationParameter1
Configuration23_Item1=Crossprobe=False|EnableAttributes=True|Record=VHDLView|SingleFile=False
OutputType24=WireListNetlist
OutputName24=WireList Netlist
OutputDocumentPath24=
OutputVariantName24=
OutputDefault24=0
OutputType25=XSpiceNetlist
OutputName25=XSpice Netlist
OutputDocumentPath25=
OutputVariantName25=
OutputDefault25=0

[OutputGroup2]
Name=Simulator Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=SIMetrix_Sim
OutputName2=SIMetrix
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=SIMPLIS_Sim
OutputName3=SIMPLIS
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0

[OutputGroup3]
Name=Documentation Outputs