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v_fpga.tan.rpt
Classic Timing Analyzer report for v_fpga
Tue May 20 16:43:02 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
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; Table of Contents ;
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v_fpga.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
v_fpga.tan.summary
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Timing Analyzer Summary
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v_fpga.fit.summary
Fitter Status : Successful - Tue May 20 16:42:46 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : v_fpga
Top-level Entity Name : v_fpga
Family : Stratix
Device :
v_fpga.asm.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
v_fpga_cmp.qrpt
[||Compilation Report||Timing Analyzer||Clock Hold: 'altpll0:inst2|altpll:altpll_component|_clk1']
COLUMN_WIDTHS=60L,274L,414L,264L,264L,90L,114L,102L,
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
v_fpga.sim.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to