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FPGA 的代码
top_fpga_demo.lso
work
top_fpga_demo.pcf
//! **************************************************************************
// Written by: Map H.39 on Fri Mar 25 06:54:49 2005
//! ***************************************************************
top_fpga_demo.ncd
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4
###5632:XlxV32DM 3fff 15e8eNqVW1tz28iO/it5mMc9DvvebaZSJUqyoooteiQ5sZ9UtuyczU4mmUoyp+rU5scvutEiAdBnK5kaNS4fGugGQLJJz/ym1NH9r1Ltb9unf3389vHL5/MX6kzZF7
top_fpga_demo.ut
-w
-g DebugBitstream:No
-g Binary:no
-g Gclkdel0:11111
-g Gclkdel1:11111
-g Gclkdel2:11111
-g Gclkdel3:11111
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:Pu
top_fpga_demo.pad
Release 7.1.01i - par H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Fri Mar 25 06:55:07 2005
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Micr
top_fpga_demo.syr
Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.78 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set
top_fpga_demo.mrp
Release 7.1.01i Map H.39
Xilinx Mapping Report File for Design 'top_fpga_demo'
Design Information
------------------
Command Line : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise
e:\demo_fpga\DEMO_FPGA