📄 top_fpga_demo.mrp
字号:
Release 7.1.01i Map H.39Xilinx Mapping Report File for Design 'top_fpga_demo'Design Information------------------Command Line : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise
e:\demo_fpga\DEMO_FPGA.ise -intstyle ise -p xc2s100e-pq208-6 -cm area -pr b -k 4
-c 100 -tx off -o top_fpga_demo_map.ncd top_fpga_demo.ngd top_fpga_demo.pcf Target Device : xc2s100eTarget Package : pq208Target Speed : -6Mapper Version : spartan2e -- $Revision: 1.26.6.4 $Mapped Date : Fri Mar 25 06:54:43 2005Design Summary--------------Number of errors: 0Number of warnings: 4Logic Utilization: Total Number Slice Registers: 335 out of 2,400 13% Number used as Flip Flops: 311 Number used as Latches: 24 Number of 4 input LUTs: 643 out of 2,400 26%Logic Distribution: Number of occupied Slices: 464 out of 1,200 38% Number of Slices containing only related logic: 464 out of 464 100% Number of Slices containing unrelated logic: 0 out of 464 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 783 out of 2,400 32% Number used as logic: 643 Number used as a route-thru: 140 Number of bonded IOBs: 40 out of 142 28% IOB Flip Flops: 3 Number of Block RAMs: 2 out of 10 20% Number of GCLKs: 3 out of 4 75% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 40,656Additional JTAG gate count for IOBs: 1,968Peak Memory Usage: 103 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol
"clk1k_BUFG" (output signal=clk1k) has a mix of clock and non-clock loads.
The non-clock loads are: Pin I2 of reg_clk1k1 Pin I3 of u5/u1/_n00281WARNING:PhysDesignRules:372 - Gated clock. Clock net u8/_n0001 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net u5/u0/_n0001 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net u4/u1/_n0001 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.Section 4 - Removed Logic Summary--------------------------------- 4 block(s) removed 8 block(s) optimized away 4 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logicThe signal "u7/datain_0_rt1" is unused and has been removed. Unused block "u7/datain_0_rt1" (ROM) removed.The signal "u7/datain_0_rt" is unused and has been removed. Unused block "u7/datain_0_rt" (ROM) removed.The signal "u7/Mmult__n0030_inst_lut2_28_rt" is unused and has been removed. Unused block "u7/Mmult__n0030_inst_lut2_28_rt" (ROM) removed.The signal "u7/Mmult__n0030_inst_lut2_8_rt" is unused and has been removed. Unused block "u7/Mmult__n0030_inst_lut2_8_rt" (ROM) removed.Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCGND u0/U0/GNDVCC u0/U0/VCCMUXCY u7/Mmult__n0030_inst_cy_0MUXCY u7/Mmult__n0030_inst_cy_27MUXCY u7/Mmult__n0030_inst_cy_36MUXCY u7/Mmult__n0030_inst_cy_54To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | GCLKIOB | INPUT | LVTTL | | | | | || button<0> | IOB | INPUT | LVTTL | | | | | || button<1> | IOB | INPUT | LVTTL | | | | | || button<2> | IOB | INPUT | LVTTL | | | | | || button<3> | IOB | INPUT | LVTTL | | | | | || clk_tlc549 | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || cs_led<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || cs_led<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || cs_tlc549 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || din_adc | IOB | INPUT | LVTTL | | | INFF | | IFD || dout_lcd<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_lcd<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_lcd<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_lcd<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_lcd<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_lcd<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_lcd<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_lcd<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dout_led<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ichose | IOB | INPUT | LVTTL | | | | | || ienter | IOB | INPUT | LVTTL | | | | | || ireset | IOB | INPUT | LVTTL | | | | | || istepa | IOB | INPUT | LVTTL | | | | | || istepb | IOB | INPUT | LVTTL | | | | | || itclk | IOB | INPUT | LVTTL | | | | | || lcdda | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || lcden | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || lcdrw | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || otclk | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || shift<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || shift<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || shift<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || shift<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || tone | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 41Number of Equivalent Gates for Design = 40,656Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 3Block RAMs = 2TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 148IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 3IOB Flip Flops = 3Unbonded IOBs = 0Bonded IOBs = 40XORs = 183CARRY_INITs = 145CARRY_SKIPs = 0CARRY_MUXes = 259Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULT_ANDs = 0MUXF5s + MUXF6s = 244 input LUTs used as Route-Thrus = 1404 input LUTs = 643Slice Latches not driven by LUTs = 0Slice Latches = 24Slice Flip Flops not driven by LUTs = 145Slice Flip Flops = 311Slices = 464F6 Muxes = 0F5 Muxes = 24Xilinx Core blkmemsp_v6_1, Coregen 7.1.01i = 1Number of LUT signals with 4 loads = 24Number of LUT signals with 3 loads = 10Number of LUT signals with 2 loads = 84Number of LUT signals with 1 load = 494NGM Average fanout of LUT = 1.74NGM Maximum fanout of LUT = 27NGM Average fanin for LUT = 3.1913Number of LUT symbols = 643⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -