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FPGA 的代码
pc2fpga.hif
Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1624
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
pc2fpga
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
#
pc2fpga.v
module pc2fpga ( rst ,
clk,
fifo_wr ,
fifo_rd ,
fifo_data,
top_fpga_demo.prj
vhdl work "mem_infor.vhd"
vhdl work "mem_inform.vhd"
vhdl work "lcd_driver.vhd"
vhdl work "button1.vhd"
vhdl work "keyboards.vhd"
vhdl work "page_step.vhd"
vhdl work "digital_clk.vhd"
vhdl work
top_fpga_demo.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net u8/_n0001 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-
top_fpga_demo.bgn
Release 7.1.01i - Bitgen H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
"top_