top_fpga_demo.drc

来自「总体演示程序DEMO_FPGA.rar」· DRC 代码 · 共 11 行

DRC
11 行
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WARNING:PhysDesignRules:372 - Gated clock. Clock net u8/_n0001 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net u5/u0/_n0001 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net u4/u1/_n0001 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.DRC detected 0 errors and 3 warnings.

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