代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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www.eeworm.com/read/141282/13024848
txt pelican crossing控制器.txt
-- Pelican Crossing Controller
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity pelcross is
port(clock, reset, pedestrian : in std_logic;
www.eeworm.com/read/139685/13139914
txt mealy1.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/139685/13139918
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/319921/13439520
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/319921/13439532
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/316203/13528457
txt mealy1.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/316203/13528458
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/312754/13605434
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/312754/13605442
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/308751/13693819
tfw top_tbw.tfw
// E:\FPGA_PROGRAM\ISE6.1\TST
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Thu May 24 09:33:28 2007
//
// Notes:
// 1) This test fixture has been automatically generated from
//